In non-volatile memories, such as with EEPROM Flash memories, it is necessary to carry out several operations to modify the state of the memory cells which alternatively apply positive and negative voltages to their gates. Memory cells are formed by MOS transistors interconnected in a matrix-like configuration. The columns or bit lines connect the drain terminals of the transistors, and the rows or word lines connect the gate terminals.
Since the gate terminals of the memory cells are connected to each other by the word lines of the matrix cells, these word lines should, each time, be discharged to ground for alternatively applying positive and negative voltages according to the type of modify, program or erase operations the cells are to undergo.
During the modify algorithm, and in particular during the erase, there are the steps of drain stress, erase verify and depletion verify in which it is necessary to discharge, each time, at least one word line whereon there is a potential of negative voltage, although all the other word lines are maintained at negative voltages.
At present, this discharge step may be by way of a simple NMOS transistor whose body terminal is connected to ground or to a negative voltage DECS, as shown in FIGS. 1 and 2. In greater detail, the example of FIG. 1 schematically shows the structure of a gate voltage regulator 1 for non-volatile memory cells incorporated in a matrix of cells of an electronic device of the known type.
The regulator 1 includes a first circuit portion 2 comprising a pair of transistors M1 and M2. The first transistor M1 is of the PMOS type, and the second transistor M2 is of the NMOS type. They are connected to each other by their respective drain and source terminals. That is, the source terminal S1 is connected to the drain terminal D2, while the drain terminal D1 is connected to the source S2.
These transistors M1 and M2 receive, on the respective terminals S1, D2, the potential VX_RAMP, while on the gate terminals the potentials TO_VX_RAMP_N and TO_VX_RAMP are respectively applied. On the body terminals of the transistors M1 and M2 the potentials WELL_PART and GND2 are respectively applied.
The other conduction terminals D1, S2 of the transistors M1, M2 are connected to ground by a discharge transistor M3 of the NMOS type which receives, on its own gate terminal, the signal TO_RAMP_N. This transistor M3 substantially forms a complementary pair with the transistor M1.
The output of the circuit portion 2 is represented by a connection line O2 which leads a voltage signal VXS_RAMP<0> towards a second circuit portion 3 of the regulator 1. This second circuit portion 3 comprises a pair of transistors M4 and M6. The first transistor M4 is of the PMOS type, and the second transistor M6 is of the NMOS type. They are connected to each other by their respective drain and source terminals. That is, the source terminal S4 is connected to the drain terminal D6, while the drain terminal D4 is connected to the source terminal S6. These transistors M4, M6 receive on the respective terminals S4, D6 the potential VX_RAMP<0>, while on the gate terminals the potentials SPSEL_N<0> and SPSEL<0> are respectively applied.
The output of the circuit portion 3 is represented by a connection line O3 which leads a voltage signal SP<0> towards a third circuit portion 4 of the regulator 1. A transistor M5 is connected to the transistor M4 and forms with it a complementary pair. The gate terminals of the transistors M4 and M5 receive the signal SPSEL_N<0>, while on the source terminal S5 of M5 a potential DECS is applied.
An inverter 5 formed by a complementary pair of transistors M7 and M8 receives on its own gate terminals the signal SPSEL_N<0>, and outputs the signal SPSEL<0> for the gate of M6. The regulator 1 is coupled to the word line WL<0> by the third circuit portion 4 which comprises the transistors M9, M10 and M11.
The transistor M9 is of the PMOS type while the other transistor M11 is of the NMOS type. These transistors are connected to each other by their respective drain and source terminals. That is, the source terminal S9 is connected to the drain terminal D11, and the drain terminal D9 is connected to the source terminal S11.
On the terminals S9 and D11 a potential SP<0> is applied which is produced by the circuit portion 3 of the regulator 1, arranged upstream with respect to the portion 4. A transistor M10 is connected to the transistor M9 and forms with it a complementary pair. The gate terminals of the transistors M9 and M10 receive the signal GP<0>, while on the source terminal S10 of M10 a potential DECS is applied.
FIG. 1 also shows the word line parasitic capacity. The prior art approach described with reference to FIG. 1 determines the presence of two drain-body PN junctions in the regions X and Y of the transistors M2 and M3 which are directly biased during all the discharge process of the word line starting from a negative potential voltage. Simulating a drain stress operative step, it is first necessary to pre-charge the Word Line CWL capacity. This word line parasitic capacity is normally identical to some hundreds of femtoFarad.
If a negative voltage of some volts is applied and the discharge to ground of the word line occurs through the transistor M3, two current peaks have been highlighted on the junctions X, source-body of the transistor M2 and Y drain-body of the transistor M3, due to the transit of the charge in the node VXS_RAMP<0> towards GND2. This represents a highly undesired effect which induces noise onto the virtual ground GND2 and affects the overall operation of the memory device as a whole.
A second known approach is shown in the example of FIG. 2 which completely corresponds to the circuit structure of FIG. 1, except for some transistors having different labels. The transistor M14, equivalent to M3 in the example of FIG. 1, has the body terminal whereon a potential DECS is applied.
This transistor is thus subjected to a body effect which, although eliminating the presence of PN junctions directly biased, does not allow a complete discharge of the word line from a negative voltage to ground. This is due to the presence of the body effect introduced by the biasing of the body terminal of the transistor M14.